`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   15:50:48 10/31/2020
// Design Name:   alu
// Module Name:   D:/_FPGA/ARC_2020/Lab3_Pipeline/sword4-test-bench/sim/sim_alu.v
// Project Name:  sword4-test-bench
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: alu
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module sim_alu;

	// Inputs
	reg [31:0] A;
	reg [31:0] B;
	reg [4:0] Shamt;
	reg [5:0] ALU_Func;

	// Outputs
	wire [31:0] res;
	wire zero;
	wire overflow;

	// Instantiate the Unit Under Test (UUT)
	alu uut (
		.A(A), 
		.B(B), 
		.Shamt(Shamt), 
		.ALU_Func(ALU_Func), 
		.res(res), 
		.zero(zero), 
		.overflow(overflow)
	);

	initial begin
		// Initialize Inputs
		A = 2;
		B = -4;
		Shamt = 3;
		ALU_Func = 0;

		// Wait 100 ns for global reset to finish
		#50; ALU_Func = 6'b100000;		// add
      #50; ALU_Func = 6'b100001;		// addu
		#50; ALU_Func = 6'b100010;		// sub
		#50; ALU_Func = 6'b100011;		// subu
		#50; ALU_Func = 6'b100100;		// and
		#50; ALU_Func = 6'b100101;		// or
		#50; ALU_Func = 6'b100110;		// xor
		#50; ALU_Func = 6'b100111;		// nor
		#50; ALU_Func = 6'b101010;		// slt
		#50; ALU_Func = 6'b101011;		// sltu
		#50; ALU_Func = 6'b000000;		// sll
		#50; ALU_Func = 6'b000010;		// srl
		#50; ALU_Func = 6'b000011;		// sra
		#50; ALU_Func = 6'b000100;		// sllv
		#50; ALU_Func = 6'b000110;		// srlv
		#50; ALU_Func = 6'b000111;		// srav
		#50; ALU_Func = 6'b001111;		// lui

		// Add stimulus here

	end
      
endmodule

